一种反熔丝FPGA的可配置传输延迟测试电路  

A Configurable Test Circuit of Propagation Delay for Antifuse FPGA

作　　者：杜涛[1] 李威[1] 晁醒 吴方明 吴华刚 刘丹[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《微电子学与计算机》2018年第2期84-88,93,共6页Microelectronics & Computer

摘　　要：为了对反熔丝FPGA进行性能评估及芯片速度等级的定级划分,提出了采用传输延迟参数测试法进行分析.针对反熔丝FPGA一次可编程及应用需求多样性的特点,设计了一种包含完整传输延迟影响因素的专用测试电路,该电路能对测试链路级数、布线长度、散出数等多方面进行差异化配置,从而形成了具有实用性和通用性的反熔丝FPGA性能评估解决方案.通过电路仿真及1.0μm CMOS ONO反熔丝工艺硅验证实测表明,该传输延迟测试电路能实际应用于反熔丝FPGA的产品开发.In order to evaluate the performance of the antifuse FPGA and classify the chip speed level, a test methodof propagation delay is proposed. Aimed at the characteristics of one time programmable and diverse applicationrequirements for the antifuse FPGA, a novel test circuit is designed, which includes the influencing factors of thepropagation delay. The circuit exhibits a variety of configurahle capacity, including the test link configuration, therouting length configuration, the fanout value configuration, etc. The performance evaluation solution for theantifuse FPGA is practical and feasible. The results of the circuit simulation and the silicon verification based on the1.0urn CMOS ONO antifuse process show that the test circuit of propagation delay is suitable for the application ofantifuse FPGA development.

关 键 词：反熔丝FPGA 传输延迟 测试电路 可配置 

分 类 号：TN47[电子电信—微电子学与固体电子学]