基于SoC FPGA抓包的电站控制系统时钟同步设计  

Clock Synchronization Design for Power Plant Control System Based on SoC FPGA Packet Capture

作　　者：刘玉升 项文蔚 王楠 王巍 LIU Yusheng,XIANG Wenwei,WANG Nan,WANG Wei（ State Nuclear Power Automation System Engineering Co. , Ltd.,Shanghai 200241, China）

机构地区：国核自仪系统工程有限公司,上海200241

出　　处：《自动化仪表》2018年第2期54-58,共5页Process Automation Instrumentation

摘　　要：为实现基于工业以太网的电站控制系统的高精度同步数据采集和控制，对时钟同步提出了较高的要求。通过分析影响时钟同步精度的因素，提出了一种基于片上系统现场可编程门阵列（SoC FPGA）抓包辅助实现电站控制系统时钟同步的硬件设计。使用SoC FPGA对IEEE 1588协议进行解析，并采用SoC FPGA和硬件描述语言设计时间戳生成器。该方法解决了在软件层获取时间戳不稳定、同步精度低等问题，降低了电站控制系统时钟同步设计的复杂度。长期测试数据表明，SoC FPGA解析和网络报文获取准确，主控制器时钟节点和从I/O设备节点间达到了微秒级的精确定时同步，事件顺序记录（SOE）精度小于1 ms。To realize precise synchronous data acquisition and control for power plant control systems based on industrial Ethernet,higher requirements of clock synchronization is necessary. Through analyzing the factors affecting the synchronization precision,the hardware design for implementing clock synchronization of power plant control system based on systemonchip fieldprogrammable gate array（SoC FPGA） packet capture is proposed. By using SoC FPGA,the IEEE 1588 protocol is analyzed,and the SoC FPGA and hardware description language are adopted to design the timestamp generator.This method solves the problems of unstability of timestamp and low accuracy of synchronization in the software layer,and it also reduces the complexity of the clock synchronization design of the power plant control system.The data of long term test show that the SoC FPGA analysis and network message capture are correct,precise timing synchronization between the master controller clock node and the slave I/O device nodes reaches microsecond level,and sequence of event （SOE） resolution is less than 1 ms.

关 键 词：核电站 控制系统 FPGA IEEE1588 精确时钟协议 事件顺序记录 时间戳 

分 类 号：TH7[机械工程—仪器科学与技术;机械工程—精密仪器及机械] TP23