A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control  

作　　者：Zongguang Yu Xiaobo Su Zhenhai Chen Jiaxuan Zou Jinghe Wei Hong Zhang Yan Xue 

机构地区：[1]Department of Microelectronics, Xidian University, Xi'an 710071, China. [2]the No. 58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China [3]School of Electronics and Information Engineering, Xi'an Jiaotong University, Xi'an 710049, China

出　　处：《Tsinghua Science and Technology》2018年第1期87-94,共8页清华大学学报（自然科学版（英文版）

基　　金：supported by National Natural Science Foundation of China under grant No.61704161;Key Project of Natural Science of Anhui Provincial Department of Education under grant No.KJ2017A396

摘　　要：A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.

关 键 词：pipelined analog-to-digital converter charge domain low power feed-forward control 

分 类 号：TN792[电子电信—电路与系统]