90nm CMOS工艺高速锁相环设计与优化  

Design and Optimization of High Speed PLL Based on 90nm CMOS Process

作　　者：王征晨 王兴华[1] 仲顺安[1] 

机构地区：[1]北京理工大学信息与电子学院,北京市硅基高速片上系统工程技术研究中心,北京100081

出　　处：《北京理工大学学报》2018年第1期58-62,共5页Transactions of Beijing Institute of Technology

基　　金：国家自然科学基金资助项目(61301006)

摘　　要：基于TSMC90nm CMOS工艺设计了一款高速锁相环.为优化锁相环整体的相位噪声及参考杂散性能,分析了差分电荷泵和LC压控振荡器的相位噪声,并且讨论了多模分频器的设计方法.高速锁相环的整体芯片版图面积为490μm×990μm.测试结果表明,在频偏1MHz处的相位噪声为-90dBc,参考杂散为-56.797dBc.A high speed phase locked loop（PLL）was designed based on TSMC 90 nm CMOS process.In order to optimize phase noise and reference spur,the main modules of PLL such as charge pump and LC voltage controlled oscillator（VCO）were analyzed and improved.The design method of multi-modulus divider（MMD）was studied in detail.The layout of the high speed PLL was optimized and whole chip area was arranged in 490μm×990μm.The testing results show that,the in-band phase noise can reach -90 dBc at 1 MHz frequency offset and the reference spur is -56.797 dBc.

关 键 词：锁相环 电荷泵 LC压控振荡器 相位噪声 

分 类 号：TN432[电子电信—微电子学与固体电子学]