HEVC帧内预测硬件结构的设计与实现  

Implementation and design of a hardware architecture for HEVC intra prediction

作　　者：陈章芬 杨秀芝[1] 陈敏 黄博 

机构地区：[1]福州大学物理与信息工程学院,福建福州350108

出　　处：《电视技术》2017年第9期20-26,共7页Video Engineering

基　　金：国家自然科学基金项目(61671153);福建省科技重大专项(2014HZ0003-3);福建省自然科学基金项目(2015J01251);福建省教育厅项目(JA14065)

摘　　要：针对HEVC帧内预测提出一种支持所有尺寸和模式的硬件结构。提出按行(列)模式遍历方式,并利用HEVC帧内预测的参考像素选择规律设计了参考像素选择电路,同时根据不同模式和像素块之间的预测规律提出了电路复用方案。仿真结果表明,本结构在FPGA Aria II平台上综合时主频可达105 MHz,且只需256个周期即可完成32×32像素块的全模式遍历。与现有结构相比,所提结构在具有更小电路面积的同时可更快实现模式选择。A hardware architecture for High Efficiency Video Coding （HEVC） intra prediction available for all sizes and modes is presented in this paper. The regularity of reference pixels selection is adopted to design a selection circuit according to the traverse order, which makes the architecture produce one row of prediction value per period under nmltiple modes. Besides, circuit reuse scheme is reached based on the connections between various modes and sizes. Simulation results show that the architecture oper- ates at 105MHz for FPGA Aria II devices, and only requires 256 cycles to？ complete the traversal？ of all modes for 32×32 sam- ple blocks. ？ The research turns out that？ both？ resource cost and？ achievement of mode selection？ are more effective than？ ex- isting？ schemes.

关 键 词：HEVC帧内预测 遍历方式 参考像素选择 电路复用 FPGA 

分 类 号：TN919.8[电子电信—通信与信息系统]