一种抛物线型内插滤波器的FPGA实现  

FPGA Implementation of a Parabolic Interpolation Filter

作　　者：李玉峰[1] 邓军[2] 曹博 李洁洁 

机构地区：[1]唐山市交通运输局交通信息管理中心,河北唐山063000 [2]西安电子科技大学电子工程学院,陕西西安710071

出　　处：《无线电工程》2018年第4期339-342,共4页Radio Engineering

摘　　要：软件无线电中,插值滤波的算法是利用DSP来实现的,虽然其执行起来可移植性较好,开发周期较短,但存在运行速度慢、效率低的问题。使用硬件来实现有诸多优点,如运行速度快、效率高、可提高数据吞吐量和降低功耗。提出一种针对该算法的硬件实现方法,将内插滤波算法适配到一个合理的VLSI体系结构中。在拉格朗日立方插值器的基础上,为获得内插估计值而采用的分段抛物线内插滤波器,采用Farrow结构来提高滤波器的运算速率,并在FPGA上仿真,运行实现。仿真结果表明该方法正确、有效。In software defined radio,the algorithm of interpolation filter is realized by DSP,which provides better portability andshorter development cycle. However,some problems exist still,such as low speed and low efficiency. The implementation of hardware has many advantages,such as fast running,high efficiency,high data throughput and low power consumption. This paper proposes a hardware implementation of the algorithm,which adapts the interpolation filtering algorithm to a reasonable VLSI architecture. Based on Lagrange cubic interpolation device,the piecewise-parabolic interpolation filter used to obtain the interpolation estimates adopts Farrow structure to improve the operation rate of the filter,and is simulated on FPGA. Simulation results show that this method is correct and available.

关 键 词：全数字接收机 内插滤波器 FARROW结构 分段抛物线 

分 类 号：TN914.4[电子电信—通信与信息系统]