MLC闪存的最小和译码算法研究  

Research on min-sum decoding algorithm for MLC flash memory

作　　者：张旋[1] 李晓强[1] 燕莎[1] 曹建民[1] ZHANG Xuan, LI Xiao-qiang, YAN Sha, CAO Jian-min(School of Higher Technical, X i ’ a n U n iv e rs i ty o f T e c h n o lo g y,X i ’ a n 7 1 0 0 8 2,C h in a)

机构地区：[1]西安理工大学高等技术学院,西安710082

出　　处：《信息技术》2018年第4期33-36,40,共5页Information Technology

基　　金：中央高校项目(GK201603016)

摘　　要：随着多级单元(Multi-Level Cell,MLC)闪存存储密度的增加,单元间干扰(Cell-toCell Interference,CCI)成为影响NAND闪存可靠性的主要噪声。针对这种情况,在深入分析MLC闪存信道模型和CCI噪声模型的基础上,利用MLC阈值电压的均匀感知策略获取闪存页中每比特的对数似然比(Log-Likelihood Ratio,LLR)信息,提出了一种MLC型NAND闪存的最小和译码算法。仿真结果表明,在MLC闪存信道下,该方法既可保证闪存单元可靠性,又具有较短闪存单元的读取时间,从而实现了译码复杂度和性能间的良好折衷。With the increase of MLC（ Multi-Level Cell） flash memory density,cell-to-cell interference（ CCI） is the dominant noise source which affects the reliability of NAND flash memory. By making a thorough analysis of MLC channel model and CCI noise model,the log likelihood ratio（ LLR） of each bit in the page is obtained from uniform sensing strategy for the threshold voltage of MLC,a min-sum decoding algorithm is presented for MLC NAND flash memory. The simulation results show that this method can ensure the reliability of flash memory,and has a short access time,so as to achieve a better tradeoff between the decoding complexity and decoding performance.

关 键 词：多级单元 低密度奇偶校验码 最小和译码算法 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]