应用于流水线ADC的LMS自适应校准算法与FPGA实现  

Research and FPGA Implementation of LMS Adaptive Calibration Algorithm for Pipelined ADC

作　　者：王巍[1] 杨皓[1] 徐媛媛 何雍春 黄孟佳 杨正琳[1] 袁军[1] 王冠宇[1] 杨峰 WANG Wei;YANG Hao;XU Yuanyuan;HE Yongchun;HUANG Mengjia;YANG Zhenglin;YUAN Jun;WANG Guanyu;YANG Feng(College of Electronics Engineering / International Semiconductor College, Chongqing Univer. of Posts and Telecommun. Chongqing 400065, P. R. China;China Nuclear Control System Engineering Co. , Ltd. , Beijing 100000, P. R. China)

机构地区：[1]重庆邮电大学光电工程学院/国际半导体学院,重庆400065 [2]中核控制系统工程有限公司,北京100000

出　　处：《微电子学》2018年第2期257-261,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61404019)

摘　　要：研究了应用于流水线模数转换器(ADC)的LMS自适应数字校准算法及其FPGA实现。该校准算法可用于校准大多数已知的误差,包括非线性运算放大器的有限增益、电容失配,以及比较器的失调等。通过Simulink软件,对一个12位160MS/s的流水线ADC进行建模。采用LMS自适应校准算法对该流水线ADC进行校准,并将算法在Virtex-5上实现了硬件设计。实验结果表明,输入信号频率为58.63MHz时,流水线ADC的无杂散动态范围(SFDR)和有效位(ENOB)分别由校准前的46.31dB和7.32位提高到校准后的82.03dB和11.12位。The least mean squares（LMS）adaptive algorithm and its FPGA implementation for the digital background calibration in pipelined analog-to-digital converters（ADC）were investigated.The LMS adaptive algorithm was used to compensate the most known errors including nonlinear gain imperfections of operational amplifiers,capacitor mismatch and comparator offset.A 12-bit 160 MS/s pipelined ADC model was established with Simulink.The proposed LMS adaptive algorithm was used for the calibration of the above pipelined ADC,and the LMS adaptive algorithm was implemented on FPGA Virtex -5 device.The experimental results showed that when the input signal frequency was 58.63 MHz,the spurious free dynamic range（SFDR）was increased from 46.31 dB to 82.03 dB,and the effective number of bits（ENOB）was improved from 7.32 bit to 11.12 bit after calibration.

关 键 词：流水线模数转换器 后台校准 LMS自适应算法 

分 类 号：TN402[电子电信—微电子学与固体电子学]