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作 者:徐辉[1] 鲁孝平 李丹青 Xu Huia;Lu Xiaopingb;Li Danqinga(a. School of Computer Science and Engineerin;b. School of Electrical and Engineering Anhui University of Science and Technology, Huainan 232001, China)
机构地区:[1]安徽理工大学计算机科学与工程学院,安徽淮南232001 [2]安徽理工大学电气与信息工程学院,安徽淮南232001
出 处:《半导体技术》2018年第5期381-387,共7页Semiconductor Technology
基 金:国家自然科学基金资助项目(61404001,61306046);国家自然科学基金面上项目(61371025);安徽省高校省级自然科学研究重大项目(KJ2014ZD12);淮南市科技计划资助项目(2013A4011)
摘 要:为了降低电路老化对数字集成电路性能的影响,提出了一种通过对比输入信号与其反向延迟信号对电路老化进行预测的传感器结构。提出的传感器结构预测部分可对组合逻辑电路进行数据失效前的老化预测,当检测到电路已发生老化致数据失效时,容错部分可对错误信号进行矫正。该结构特殊的设计减小了面积开销和功耗。采用HSPICE软件对传感器功能进行模拟仿真,实验结果验证了传感器可在不同环境下正确地预测电路的老化情况,并对已发生错误的信号进行矫正,与其他功能相同的传感器相比,该传感器的面积及功耗分别降低了30.91%和41.3%。In order to reduce the influence of circuit aging on the performance of digital integrated circuits,a sensor was proposed to predict the aging of the circuit by comparing the input signal and its reverse delay signal. The aging of the combinational logic circuit can be predicted by the proposed sensor before the data failure. When the circuit has been degraded and the data are invalid,the fault tolerance part can be used to correct the error signal. The special design of this structure saves chip area and power consumption. Based on HSPICE software,the function of the sensor was simulated,and the experimental results verify that the sensor can precisely predict the aging of the circuit in different situations,and correct the wrong signal. Compared with other sensors with the same function,the area and power consumption are reduced by 30. 91% and 41. 3%,respectively.
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