Low-Complexity Detection and Decoding Scheme for LDPC-Coded MLC NAND Flash Memory  被引量:1

Low-Complexity Detection and Decoding Scheme for LDPC-Coded MLC NAND Flash Memory

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作  者:Xusheng Lin Guojun Han Shijie Ouyang Yanfu Li Yi Fang 

机构地区:[1]School of Information Engineering, Guangdong University of Technology [2]National Mobile Communications Research Laboratory, Southeast University

出  处:《China Communications》2018年第6期58-67,共10页中国通信(英文版)

基  金:supported in part by the NSF of China (61471131, 61771149, 61501126);NSF of Guangdong Province 2016A030310337;the open research fund of National Mobile Communications Research Laboratory, Southeast University (No. 2018D02);the Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme (2017-ZJ022)

摘  要:With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.

关 键 词:Cell-to-cell interference(CCI) LDPC codes MLC NAND flash memory non-uniform detection(N-UD) modified soft reliability-based iterative majority-logic decoding(MSRBI-MLGD) algorithm 

分 类 号:TP333[自动化与计算机技术—计算机系统结构] TN911.22[自动化与计算机技术—计算机科学与技术]

 

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