基于55 nm CMOS工艺的2.5 Gbit/s高灵敏度跨阻放大器  

A 2.5 Gbit/s High Sensitivity Transimpedance Amplifier Based on 55 nm CMOS Technology

作　　者：余得水 何进[1] 陈伟[1] 王豪[1] 常胜[1] 黄启俊[1] 童志强 YU Deshui;HE Jin;CHEN WeiI;WANG Hao;CHANG Sheng;HUANG Qijun;TONG Zhiqiang(School of Physics and Technology, Wuhan University, Wuhan 430072, P. R. China;Wuhan Fisilink Microelectronic Technology Ltd. , Wuhan 430200, P. R. China)

机构地区：[1]武汉大学物理科学与技术学院,武汉430072 [2]武汉飞思灵微电子技术有限公司,武汉430200

出　　处：《微电子学》2018年第3期289-294,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61774113;61574102;61404094);中央高校基本科研资助项目(2042014kf0238);中央高校基本科研业务费专项资金资助项目(2042017gf0052);中国博士后科学基金资助项目(2012T50688)

摘　　要：基于55nm CMOS工艺,设计了一种工作速率为2.5Gbit/s的高灵敏度跨阻放大器(TIA)。TIA输入级电路采用三级反相器级联结构。为了提高动态范围,采用了双自动控制增益(AGC)电路来调节反馈电阻阻值。输入级电路后级的三级差分放大器进一步放大电压信号,并运用有源电感峰化技术来提高带宽,最后进行缓冲器输出。为了降低跨阻放大器的噪声,设计了基准带隙电路和电压偏置电路,采用温度补偿技术来保证芯片的温度稳定性。电路仿真结果表明,在误码率BER=1×10-12情况下,TIA的后仿真灵敏度为-30.2dBm,跨阻增益为87.5dBΩ,带宽为1.8GHz。在3.3V电压的条件下,功耗为119.4mW。A high sensitivity transimpedance amplifier（TIA）working at 2.5 Gbit/s was designed in a 55 nm CMOS process.The input stage was based on a 3-stage inverting voltage amplifier.A double-AGC circuit was utilized to improve the dynamic range by controlling the feedback resistors.The input stage was followed by a 3-stage differential amplifier to amplify the voltage signals,and an active inductive peaking technique was used to expand the bandwidth.The last stage was the output buffer.Furthermore,the bandgap references and voltage bias circuits were implemented to reduce the TIA＇s noise,and the temperature compensation technique was used to ensure the thermal stability of the chip.The simulation results showed that the post layout simulated optical sensitivity was-30.2 dBm for a BER =1×10^-12.The complete chip achieved a transimpedance gain of 87.5 dBΩand a bandwidth of 1.8 GHz.The power consumption of the TIA was 119.4 mW at 3.3 Vsupply voltage.

关 键 词：高灵敏度 跨阻放大器 双AGC电路 有源电感峰化 温度补偿 

分 类 号：TN722[电子电信—电路与系统] TN432