一种基于维纳延迟环的高线性度TDC  

A High Linearity Time-to-Digital Converter Based on Vernier Delay Loop

作　　者：王巍[1] 何雍春 徐媛媛 杨皓[1] 周凯利 袁军[1] 杨正琳[1] 王冠宇[1] WANG Wei;HE Yongchun;XU Yuanyuan;YANG Hao;ZHOU Kaili;YUAN Jun;YANG Zhenglin;WANG Guanyu(College of Optoelec. Engineer. ~Int. Semicond. College, Chongqing Univ. of Posts and Telecornm. , Chongqing 400065, P. R. Chin)

机构地区：[1]重庆邮电大学光电工程学院/国际半导体学院,重庆400065

出　　处：《微电子学》2018年第3期326-331,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61404019)

摘　　要：设计了一种基于维纳延迟环的时间数字转换器(TDC)。该TDC基于TSMC 0.18μm CMOS工艺进行设计,实现了高分辨率和高线性度。采用一种新型环形传播延迟结构来代替时钟信号,相比传统结构,减少了1组粗-精2级插值器的使用。粗计数器由该新型环形传播延迟结构和6位计数器构成,实现了输入的START信号与周期信号同步,测量动态范围达到208ns。粗-精2级插值器中,第1级由粗插值器和同步器构成,第2级是一个基于单阶维纳环的精插值器。利用维纳环的循环滑动测量技术,有效提高了TDC的转换线性度。仿真结果表明,该TDC的分辨精度可达10ps,微分非线性低于20ps,积分非线性低于30ps。A time-to-digital converter（TDC）with Vernier delay ring was designed in TSMC 0.18μm CMOS process.It achieved high precision and high linearity.The TDC circuit adopted a new type of circular propagation delay structure instead of the clock signal.Compared with the traditional structure,one set of coarse-fine two stage interpolator was reduced.The coarse counter was based on this new type of circular propagation delay structure and a 6-bit counter,so that the START signal was synchronous to the periodic signal,and the coarse counter resulted in a dynamic time measuring range of 208 ns.The first stage of the coarse-fine two stage interpolator was built with a coarse interpolator and synchronizer.The second stage was a fine interpolator which was built with a single-order Vernier delay loop.The cyclic sliding scale technique was employed,so the conversion linearity had been improved effectively.The simulation results showed that the proposed TDC could reach a resolution of 10 ps.The differential non-linearity was lower than 20 ps,and the integral non-linearity was lower than 30 ps.

关 键 词：时间数字转换器 粗计数器 插值器 维纳延迟环 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN79