一种基于平均电阻网络的预放大级设计  

Design of a Pre-amplifier Based on Average Resistance Network

作　　者：曾凤姣 邓红辉[1] 卫海燕 ZENG Fengjiao;DENG Honghui;WEI Haiyan(Institute of VLSI Design, Hefei University of Technology, Hefei 230009, P. R. Chin)

机构地区：[1]合肥工业大学微电子设计研究所,合肥230009

出　　处：《微电子学》2018年第3期374-380,共7页Microelectronics

基　　金：中央高校基本科研业务费专项资金资助项目(JD2016JGPY0003)

摘　　要：平均电阻网路的引入会给预放大器带来增益、延时误差、边界效应等问题。通过从中间向两边依次增加预放大器输入对管的尺寸,减小整体误差。通过改变环形平均电阻的边界阻值和边缘放大器的输入参考电压,减小边界效应,并且使用的边缘放大器数目较少。采用TSMC 0.18μm标准CMOS工艺,在1.8V电源电压下,对加入平均电阻网络的ADC的输出进行仿真,得到INL为1.01LSB、DNL为0.573LSB。对改变输入对管尺寸的ADC整体电路进行DFT分析,得到ENOB为11.14bit、SFDR为76.3dB、THD为-78dB。采用减小边界效应的方法,对边界预放大器进行蒙特卡洛仿真,结果表明,失调电压方差从2.193mV减小到0.456mV。The addition of average resistance network will bring some troubles of gain error,delay error,boundary effect to the pre-amplifiers.The total errors were reduced by increasing the size of differential input pairs of the pre-amplifier from the pair＇s middle to both sides.The boundary effect was reduced by changing the boundary resistance of ring average resistor and the input reference voltage of edge amplifier.The required number of edge amplifier was small.The proposed average resistance network was employed in a ADC.The output of ADC was simulated in TSMC 0.18μm standard CMOS process at a power supply voltage of 1.8 V.The simulation results showed that the INL was 1.01 LSB and the DNL was 0.573 LSB.The overall ADC circuit that the size of differential input pairs was changed in the pre-amplifier had been analyzed by DFT.The results showed that the ENOB was 11.14 bit,the SFDR was 76.3 dB and the THD was-78 dB.Using the method of reducing the boundary effect,the boundary pre-amplifier was simulated by Monte Carlo scheme,and the variance of offset voltage was reduced from 2.193 mV to 0.456 mV.

关 键 词：模数转换器 预放大器 平均电阻 边界效应 

分 类 号：TN792[电子电信—电路与系统]