基于改进DA算法的高效FIR滤波器设计  

Design of High-efficient FIR Filter Based on Improved Distributed Arithmetic

作　　者：李建军[1] 沈三民[1] 刘勇良 刘文倩 LI Jian-jun,SHEN San-min,LIU Yong-liang,LIU Wen-qian(North University of China,Key Laboratory of Instrumentation Science ＆ Dynamic Measurement,Ministry of Education,Taiyuan 030051,Chin)

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室,山西太原030051

出　　处：《仪表技术与传感器》2018年第5期39-42,69,共5页Instrument Technique and Sensor

基　　金：国家自然科学基金重点项目(61335008)

摘　　要：针对当前分布式算法(DA)实现高阶FIR滤波器,存在硬件资源占用多和功耗高的缺点,提出一种低功耗、低面积的改进算法。在无查找表结构的基础上,将采样数据最高位从移位寄存器首先输出,部分和累加由传统的右移变为左移。其次,在数据选择器的输入端添加三态缓存器,减少了加法器的翻转次数。为验证改进算法的高效性,设计不同阶长的FIR滤波器,在ISE平台对硬件代码进行综合仿真。结果表明,改进DA算法相比传统DA算法,逻辑单元和存储器占用分别减少38.44%、83.72%,功耗降低26.12%。Aiming at the disadvantages of high hardware resources consumption and high power consumption of the current high-order FIR filters achieved by the distributed algorithms（ DA）,an improved low-power and low-area algorithm was proposed.On the basis of no look-up table structure,the highest bit of sampling data was output from the shift register first,and the accumulations of partial sum were changed from the traditional right shift to the left shift.Second,adding a tristate buffer to the input of the data selector reduced the number of flip-flops of the adder.To verify the efficiency of the improved algorithm,different lengths FIR filters were designed,and the hardware code was simulated on the ISE platform.The results show that compared with the traditional DA algorithm,the occupancy of logic cells and memory are reduced by 38.44% and 83.72% respectively,and the power consumption decreases 26.12%.

关 键 词：分布式算法 FIR滤波器 查找表 数据选择器 三态缓存器 

分 类 号：TN713[电子电信—电路与系统]