基于FPGA的图像接口的设计  

Design of Image Interface Based on FPGA

作　　者：韩众 李智中 曹飞 Han Zhong;Li Zhizhong;Cao Fei(School of Instruments and Electronics, Zhongbei University, Taiyuan Shanxi 030051;Beijing Institute of Long-March Aerospace Vehicles, Beijing 100076)

机构地区：[1]中北大学仪器与电子学院,山西太原030051 [2]北京航天长征飞行器研究所,北京100076

出　　处：《现代工业经济和信息化》2018年第5期37-39,97,共4页Modern Industrial Economy and Informationization

摘　　要：设计了一种基于FPGA控制的图像接口,前端CMOS摄像头利用SCCB协议接口获取图像数据,中端利用FIFO和SDRAM构建的二级存储结构实现图像数据的乒乓式存储,终端利用VGA接口实时显示的方案。设计前端利用FPGA作为主控制器,通过SCCB协议接口配置640*480分辨率的CMOS摄像头寄存器;中端将持续输出的图像数据通过WFIFO缓存写入SDRAM中,再通过RFIFO缓存读出SDRAM中的图像数据,其中对SDRAM的读写采用乒乓式结构以解决图像拖影问题;终端FPGA设计严格的VGA时序接口接收RFIFO缓存图像数据,最终实现32MB/s图像数据的VGA实时显示。An image interface based on FPGA control is designed. The front-end CMOS camera uses the SCCB protocol interface to obtain image data, and the middle end uses the secondary storage structure constructed by FIFO and SDRAM to realize the ping-pong storage of image data. The terminal uses the VGA interface to display in real time. The design front end uses FPGA as the main controller, configures the 640 N480 resolution CMOS camera register through the SCCB protocol interface, the middle end writes the continuously output image data to the SDRAM through the WFIFO cache, and then reads out the SDRAM through the RFIFO cache. Among them, the ping-pong structure is used to read and write SDRAM, and the terminal FPGA designs strict VGA timing interface to receive the RFIFO cache image data, and finally realizes the VGA real-time display of 32 MB/s image data.

关 键 词：FPGA SCCB SDRAM FIFO CMOS 实时显示 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]