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作 者:周强[1] 田帅帅 张秋爽 ZHOU Qiang;TIAN Shuai-shuai;ZHANG Qiu-shuang(School of Automation Science and Electrical Engineering, B UAA, Beijing 100191, China;Beijing Central Department of Mechanical and Electrical Engineering Design, Beijing 100854, China)
机构地区:[1]北京航空航天大学自动化科学与电气工程学院,北京100191 [2]北京机电工程总体设计部,北京100854
出 处:《电子设计工程》2018年第11期72-76,共5页Electronic Design Engineering
摘 要:反射内存网络因其高速、可靠及可预测性的特点为多主机测试系统提供了高效的解决方案。现有的反射内存网络集线器多以高速数据选择器为核心器件或基于FPGA配合8路高速串并/并串转换芯片来实现。针对其布线难度大,且易受并行线线间串扰影响产生误码的问题,采用硬件集成了高速收发器的FPGA,设计并实现了一种基于Xilinx GTP核的高速反射内存集线器。最后,通过对集线器构成的环型和星型拓扑结构传输延时的测试试验,验证了该集线器的稳定性与实时性。The reflective memory network provides an efficient solution for multi-host test with its highspeed,reliable and predictable features. The existing reflect memory network is still built with highspeed multiplexer as core component or based on FPGA with 8-channel high-speed Serializer/Deserialzer chip. As its traces are difficult and susceptible by crosstalk between parallel to generate error code,a high-speed reflective memory network hub based on Xilinx GTP core is designed and realized using the FPGA which integrated with high-speed transceiver. Finally,the stability and real-time performancesof the hub are verified by the transaction delay test for ring and star topology structures composed of the hub.
关 键 词:反射内存网络 星型拓扑结构 集线器 高速串行收发器
分 类 号:TN06[电子电信—物理电子学]
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