基于FPGA的并行脉冲压缩算法设计与实现  

Method of reinforcement and detection in FPGA implementation of pulse compression algorithm

作　　者：王珊珊 韩文俊[1] 吴沁文[1] Wang Shanshan;Han Wenjun;Wu Qinwen(Nanjing Institute of Electronic Technology, Nanjing 210013, China)

机构地区：[1]南京电子技术研究所

出　　处：《国外电子测量技术》2018年第1期69-73,共5页Foreign Electronic Measurement Technology

摘　　要：针对雷达系统中对脉冲压缩算法日益提高的实时性要求,文章设计实现了基于FPGA的并行流水的脉冲压缩。脉冲压缩算法在设计中基于DIT和DIF的FFT并行处理架构,相邻蝶形运算单元复用RAM,处理延时小,点数可参数配置。给出了整个脉压模块的并行流水架构和实现方案,给出了系统设计的硬件结构。仿真验证了结果的正确性,并对资源占用等指标进行了有效性评估。经过理论分析和实现结果表明,设计的脉冲压缩模块能获得比传统调用IP核实现的脉冲压缩模块更好的系统实时性和更小的资源占用率。Based on FPGA in space radiation environment are prone to occur single event upset,in turn,affects the stability of the system,paper add the reinforcement design and monitoring of the pulse compression algorithm.According to the characteristics of the algorithm and reinforcement requirements,FFT module was designed to reduce the system delay of the algorithm and then meet the real-time requirements of satellite borne system.The key register module and finite-state machine（FSM）,adopt a variety of reinforcement measures,and the pulse compression module adopt a variety of monitoring methods such as timeout handling and sum-checking processing.These methods can correct one bit flip mistakes real-time,improve the fault tolerance of the system,and implement the reinforcement and monitor of pulse compression algorithm

关 键 词：脉冲压缩算法 存储复用 并行流水 实时性 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]