一种采用新型逻辑算法的SAR ADC  

An SAR ADC Using A New Type of Logical Algorithm

作　　者：黄添益 王本艳 景蔚亮 宋志棠[1,2,3] 陈邦明 HUANG Tian-yi;WANG Ben-yan;JING Wei-liang;SONG Zhi-tang;CHEN Bang-ming(State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Shanghai 200050, China;School of Physical Science and Technology, Shanghai Tech University, Shanghai 201210, China;Shanghai Xinchu Integrated Circuit Inc. , Shanghai 201500, China;University of Chinese Academy of Sciences, Beijing 100049, China)

机构地区：[1]中国科学院上海微系统与信息技术研究所信息功能材料国家重点实验室,上海200050 [2]上海科技大学物质科学与技术学院,上海201210 [3]中国科学院大学,北京100049 [4]上海新储集成电路有限公司,上海201500

出　　处：《微电子学与计算机》2018年第7期35-40,共6页Microelectronics & Computer

基　　金：国家重点研发计划(2017YFA0206101)

摘　　要：基于SMIC 40nm CMOS工艺,设计了一种12位逐次逼近寄存器式模数转换器(SAR ADC).在正常工作模式的基础上,增加了当模拟输入信号变化缓慢时,锁定前4位,仅转换后8位的工作模式,降低了ADC的功耗,提高了ADC的采样率,同时分辨率保持不变.当模拟输入信号变化较大时,ADC又可重新回到正常工作模式.在1.1V的电源电压,3.6 MS/s的采样率下,ADC总功耗为43μW,品质因数FOM为10.1fJ/(conv.·step).A 12-bit successive-approximation-register analog-to-digital converter （SAR ADC） was designed in SMIC 40nm CMOS process. Base on traditional SAR logic, add an algorithm of when analog input signal changes slowly, ADC locking its first 4 bits, and only do last 8 conversions. And when analog input signal has great change, ADC returns to normal working mode. It decreases power consumption and increase sampling rate of ADC, but doesn＇t change resolution of ADC. Under a 1.1V supply and 3. 6 MS/s sampling rate, the total power consumption of is 43 μW, and the FOM is 10. lfJ/（conv. · step）.

关 键 词：逐次逼近寄存器式模数转换器 新型SAR逻辑 锁定ADC前几位 低功耗ADC 

分 类 号：TN432[电子电信—微电子学与固体电子学]