一种高可靠SoC芯片的系统级设计方法  

A System Design Methodology for High Reliable SoC

作　　者：柳泽辰 蒋剑飞[1] 王琴[1] 关宁 LIU Ze-chen;JIANG Jian-fei;WANG Qin;GUAN Ning(School of Microelectronics, Shanghai Jiao Tong University, Shanghai 200240, China;Shanghai Aerospace Electronics and Communication Equipment Research Institute, Shanghai 201108, China)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240 [2]上海航天电子通讯设备研究所,上海201108

出　　处：《微电子学与计算机》2018年第7期54-57,共4页Microelectronics & Computer

基　　金：上海航天科技创新基金(SAST201355)

摘　　要：为了实现SoC在系统级的高可靠设计,文本搭建了一个包括PowerPC、DRAM、DMA、SRAM模块的SoC系统级设计平台,并采用VCI总线协议实现互连.针对高可靠性问题,本文提出并实现了三模冗余与ECC纠错编码相结合的存储加固方法,通过一个图像数据处理程序,分析比较了利用冗余和编码带来的可靠性提升.系统级仿真结果表明,本文提出的高可靠设计可以显著提高SoC的可靠性.In this paper, the reliability problem of the SoC is analyzed in system level. In order to implement the high reliable SoC in system level, a SoC system is designed which includes VCI bus, PowerPC processor, DMA controller, SRAM and DRAM interfaces. As for the high reliable SoC, this paper proposed a high reliable storage mechanism based on a TMR and ECC hybrid structure. An image processing program is design to simulate the reliability of the SoC system in system level. The simulation result shows that the proposed high reliable structure can improve the reliability of the SoC system.

关 键 词：系统级芯片 三模冗余 错误检测和纠正 电子系统级设计 高可靠 

分 类 号：TN4[电子电信—微电子学与固体电子学]