基于FPGA的GTX片内环回的设计与测试  

Design and test of GTX on chip loopback based on FPGA

作　　者：朱庆之 Zhu Qingzhi(School of Computer and Information, Hohai University, Nanjing 211100, China)

机构地区：[1]河海大学计算机与信息学院

出　　处：《电子测量技术》2018年第5期128-131,共4页Electronic Measurement Technology

摘　　要：随着目前信号传输速率和信号完整性的要求越来越高,信息数据的交互传输也越来越重要。GTX作为一种低功耗的吉比特收发器,配置灵活,功能强大,并与FPGA内部的其他逻辑资源紧密联系,可用于实现多种高速接口,如XAUI、PCIE等。研究利用Virtex-7系列FPGA实现了GTX的IP控制器、用户接口模块的设计,参数及测试数据的封装,并在硬件测试平台测试,最终通过VIVADO的Debug功能进行在线下载功能测试验证,实验结果表明该IP控制器下的数据在内部环路中能够进行稳定的无差错传输。With the signal transmission rate and signal integrity requirements are getting higher and higher,the interactive transmission of information and data is more and more important.The GTX,a low-power,gigabit transceiver,is flexible,powerful,and tightly coupled with other logic resources within the FPGA for a variety of highspeed interfaces such as XAUI,PCIE,and more.The design of GTX IP controller and user interface module and the parameters and test data package are encapsulated by Virtex-7 series FPGAs and tested in the hardware test platform.Finally,VIVADO′s Debug function is used to verify the online download function test.The experimental results show that the data under the IP controller can be stably and error-freely transmitted in the loopback.

关 键 词：GTX IP控制器 VIVADO DEBUG 内部环路 

分 类 号：TN914.3[电子电信—通信与信息系统]