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作 者:董坤 方振国[1] DONG Kun,FANG Zhenguo(School of Physics and Electronic Information,Huaibei Normal University,235000,Huaibei,Anhui,Chin)
机构地区:[1]淮北师范大学物理与电子信息学院,安徽淮北235000
出 处:《淮北师范大学学报(自然科学版)》2018年第2期26-32,共7页Journal of Huaibei Normal University:Natural Sciences
基 金:安徽省质量工程项目(2016zy109;2015tszy014;2014xnzx009)
摘 要:针对传统时序电路中存在的冗余时钟信号问题,分析冗余时钟信号在系统中的产生条件及分布情况.研究将基于算法优化与基于电路控制的两种门控技术相融合,提出一种新的低功耗时序电路设计方法.该方法在优化算法上,引入行为卡诺图的分析设计理念,直观展现出电路中每个触发器的冗余时钟信号的分布.在电路结构上,以与非门、或门及异或门建立基本门控电路模型,抑制保持"0"或保持"1"状态下的无效触发,有效释放"α"或"β"跃变,尽可能消除系统中的冗余时钟,实现有效降低电路整体功耗的目的.文章以4位扭环型计数器为设计实例,经Quartus ii仿真测试,结果表明采用新方法设计的电路逻辑功能正确,能够实现自启动.与传统设计方法相比,能够节省更多的功耗或者提升电路性能,证明该方法的有效性和优越性.Aiming at the problem of redundant clock signals in traditional sequential circuits,the conditionsand distribution of redundant clock signals are analyzed in the system. The research combines two kinds ofgating technologies based on algorithm optimization and circuit control,and proposes a new design methodfor low-power sequential circuit. In the optimization of algorithm,the method ntroduces the analysis and de.sign concept of behavioral Karnaugh map,and visually displays the distribution of the redundant clock signalof each trigger in the circuit. In the circuit structure,a model of gating circuits is developed based on NANDOR and XOR logic structure. Gate two kinds of holding behaviors of“0”or“1”and gain transition behav.iors of“α”or“β”,as much as possible to eliminate redundant clock system,and to achieve the purpose ofreducing the overall power consumption of the circuit. Finally,four twisted ring counter as practical designexamples using this new method are studied and simulated by Quartus ii. Simulation shows that the newmethod has correct logic function and can self-start. Compared with the traditional design method,it cansave more power or improve the circuit performance,which proves the effectiveness and superiority of thismethod.
分 类 号:TN402[电子电信—微电子学与固体电子学]
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