一种宽带接收机射频前端芯片设计  

Design of RF Front-end Chip for Wideband Receiver

作　　者：竺磊 吴俊杰[1] 万川川[1] 张浩[1] ZHU Lei;WU Junjie;WAN Chuanchuan;ZHANG Hao(Nanjing Research Institute of Electronics Technology,Nanjing 210039,China)

机构地区：[1]南京电子技术研究所,南京210039

出　　处：《微处理机》2018年第3期15-19,共5页Microprocessors

摘　　要：设计了一种适用于0.2~4GHz雷达系统的宽带接收机射频前端芯片,采用台积电0.18-μm Bi CMOS工艺流片。芯片内部集成了低噪声放大器,下变频混频器,片内低通滤波器,采用三阶项抵消技术实现高线性度的中频放大器。芯片的高集成度和高线性度适应现代雷达的小型化、高动态的要求。测试结果显示,芯片实现了3d B噪声系数、35d B功率增益、40d Bm输出三阶交调点、20d Bm输出1d B压缩点的性能。芯片在5V工作电压下,消耗220m A电流。In this paper, a wideband receiver RF front-end chip for 0.2 -4 GHz radar system is designed, which uses 0.18-μm Bi CMOS process of TSMC to realizing chip manufacturing. Low-noise amplifier, down-conversion mixer and on-chip low-pass filter are integrated in the chip, and the high linearity IF amplifier is realized by using third-order term cancellation technology. The high integration and linearity of the chip adapt to the miniaturization and high dynamic requirements of modern radar.The test results show that the chip achieves 3 d B noise figure, 35 d B power gain, 40 d Bm output third-order intermodulation point and 20 d Bm output 1 d B compression point. The chip consumes 220 m A of current at 5 V operating voltage.

关 键 词：接收机 射频前端 低噪声放大器 下混频器 低通滤波器 三阶项抵消 

分 类 号：TN47[电子电信—微电子学与固体电子学]