面向MLC STT-RAM的寄存器分配策略优化研究  

Optimization of Register Allocation Strategy for MLC STT-RAM

作　　者：倪园慧 陈巍文 王磊 邱柯妮[1,2] NI Yuan -hui1,CHEN Wei- wen1, WANG Lei1, QIU Ke-ni1,2(1College of Information Engineering, Capital Normal University, Beijing 100048, China;2Beijing Advanced Innovation Center for Imaging Technology,Beijing 100048 ,Chin)

机构地区：[1]首都师范大学信息工程学院,北京100048 [2]北京成像技术高精尖创新中心,北京100048

出　　处：《计算机科学》2018年第B06期562-567,共6页Computer Science

基　　金：国家自然科学基金(61502321);北京市教委一般项目(KM201710028016);北京市大学生"实培计划"资助基金资助

摘　　要：多级自旋转移力矩磁性存储器(MLC STT-RAM)是一种新型的非易失性存储介质。不同于采用电荷方式来存储信息的SRAM,MLC STT-RAM利用自旋偏振电流通过磁隧道结(MTJ)改变自由层的磁层方向来存储信息,能够天然地避免电磁干扰。文章利用MLC STT-RAM的抗电磁辐射特性,探索在航天抗辐照环境下将其作为存储介质用于寄存器设计。在MLC STT-RAM中,每个存储单元有4种不同的阻抗状态,不同的阻抗状态之间的转换具有不同的能耗和延迟的代价。而传统的基于SRAM的寄存器分配技术并没有考虑不同的写状态转换的影响,其在没有考虑溢出优先级的情况下启发式地选择潜在溢出变量,因此该方法不适合用在MLC STT-RAM的寄存器分配中。针对该问题,提出了一种面向写状态转换的MLC STT-RAM寄存器分配的溢出优化策略。具体来说,首先,通过每个写状态转换频率的线性组合来构成溢出代价模型。然后,根据溢出代价模型针对性地选择溢出变量,选择代价低的变量保存在寄存器中,而代价高的变量倾向于被溢出,从而便实现了面向MLC STT-RAM的寄存器分配策略的优化设计。Multi-level cell spin-transfer torque random access memory（MLC STT-RAM）is a promising nonvolatile memory technology.Unlike the SRAM that uses a charge mode to store information,MLC STT-RAM uses the spin polarization current to change the magnetic layer direction of the free layer through the magnetic tunneling junction（MTJ）to store information,so it can naturally avoid electromagnetic interference.This paper used the anti-electromagnetic radiation characteristics of MLC STT-RAM,and explored it as a register for its natural immunity to electromagnetic radiation in rad-hard space environment.MLC STT-RAM exhibits unbalanced write-state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped.This feature leads to nonuniform costs of write-states in terms of latency and energy.However,current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write-state transition costs.As a result,those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM.Aiming to address this limitation,this paper proposed a state-transition aware spilling cost minimization（SSCM）policy to save power when MLC STT-RAM is employed in register design.Specifically,the spilling cost model is first constructed according to the linear combination of different state transition frequencies.Directed by the proposed cost model,the compiler picks up spilling candidates with the highest cost to achieve lower power and higher performance.

关 键 词：MLC STT-RAM 写状态转换 潜在溢出 寄存器分配 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]