超深亚微米导航SoC芯片的低功耗策略  

Research on Low Power Technology of Ultra-Deep Submicron GNSS SoC

作　　者：张文华[1] ZHANG Wenhua

机构地区：[1]中国电子科技集团公司第二十研究所,西安710068

出　　处：《现代导航》2018年第3期183-187,共5页Modern Navigation

摘　　要：作为导航技术发展的主要方向之一,导航SoC芯片的功耗对系统各方面有巨大的影响。本文对SoC芯片的动态功耗、静态功耗和存储器功耗从原理上进行了分析,并从系统级、行为级、RTL级、门级和物理级分别研究了低功耗设计实现技术。As one of the main point of GNSS technology, the power of GNSS SoC impacts the system strongly. The dynamic power, statistics power and memory power has been analyzed in principle in this paper, and the low power design technology has been studied in system level, action level, RTL level, gate level and physical level.

关 键 词：导航SoC芯片 低功耗设计 

分 类 号：TN47[电子电信—微电子学与固体电子学]