基于多级队列缓存淘汰算法的处理器全数字仿真优化  

Dynamic Instruction Translation Based Processor Full Digital Simulation optimization

作　　者：范延芳[1] 韦涌泉 王向晖[1] Fan Yanfang, Wei Yongquan, Wang Xianghui(Beijing Institute of Spacecraft System Engineering, Beijing 100094, Chin)

机构地区：[1]北京空间飞行器总体设计部,北京100094

出　　处：《计算机测量与控制》2018年第6期180-183,共4页Computer Measurement &Control

摘　　要：通过虚拟目标机实现星载软件的测试是节约卫星开发成本,提高卫星软件测试效率的重要手段;作为星载计算机的核心部件,虚拟处理器的指令集执行速度直接决定虚拟目标机的仿真效率;采用多级队列缓存淘汰策略对QEMU原有的动态指令翻译实现进行优化,提高仿真处理器的执行效率,因此若采用仿真处理系统加载星载嵌入式软件进行测试,可以根据测试需要,在仿真处理器可实现范围内加速运行被测软件,从而实现缩短软件测试周期的目的;选取某星载中心计算机嵌入式应用软件为测试对象,实验表明,采用优化算法后的仿真处理器的运行速度可以达到平均260 MIPS,是QEMU-2.6.1版未优化前实现的仿真处理器处理速度的9.3倍,即,采用仿真处理器能够使被测软件运行在9倍于硬件处理器的运行速度下,大大提升了软件测试效率,缩短了测试周期。Flight software testing with virtual target machine may decrease Satellite development costs and increase the product＇s quality.During the development of flight software,the processor emulator is an essential tool for software development,verification and the core component of the satellite simulator,which can be substituted for the real hardware.A BM3803 processor simulation method based on optimiezed dynamic instruction translation is proposed,in which,multi queue algorithm is applied to optimize cache elimination strategy.Experimental results show that,after the opitimiztion,the processing speed of the optimized process emulator may reach 260 MIPS on average,whichi is 9.6 times of the speed of process emulator provided by QEMU 2.6.1 version.Comparing with the testing speed given by the hardware system,the testing system developed by with the emulator may increase the testing speed by 9 times.

关 键 词：动态指令翻译 多级队列缓存淘汰算法 处理器仿真 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]