基于SoC FPGA的北斗接收机载波跟踪环路设计  

Design of carrier tracking loop for Beidou receiver based on SoC FPGA

作　　者：韦照川[1] 潘军道 吴国增 Wei Zhaochuan;Pan Jundao;Wu Guozeng(School of Information and Communication,Guilin University of Electronic Technology,Guilin 541004,China)

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《电子技术应用》2018年第6期124-128,共5页Application of Electronic Technique

基　　金：国家自然科学基金(61771150);桂林电子科技大学研究生创新计划(2016YJCX84);广西精密导航技术与应用重点实验室基金(GXKL0614107)

摘　　要：为了实现北斗卫星导航接收机高实时性、小型化及低功耗,提出了一种基于SoC FPGA的载波跟踪环路的设计方案。通过对FLL(锁频环)和PLL(锁相环)的分析,并利用SOPC技术,实现了基于SoC FPGA的载波跟踪环路,可完全在FPGA内部完成载波的剥离。测试结果表明,该方案能实现载波信号的快速精确跟踪,具有良好的实时性和应用价值。In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver,a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA.The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and applica-tion value.

关 键 词：北斗卫星导航接收机 载波跟踪环路 SOC FPGA 

分 类 号：TN927[电子电信—通信与信息系统]