Stratus HLS工具在高性能双精度浮点乘法设计中的应用流程  

The application flow of Stratus HLS tool in high performance double precision floating point multiplication design

作　　者：苑佳红 Yuan Jiahong(Phytium Technology Co.,Ltd.,Changsha 410000,China)

机构地区：[1]天津飞腾信息技术有限公司,湖南长沙410000

出　　处：《电子技术应用》2018年第8期20-23,30,共5页Application of Electronic Technique

摘　　要：双精度浮点乘法部件是高性能CPU的核心运算部件之一。描述了使用Cadence Stratus HLS工具设计和实现双精度浮点乘法部件,探索新设计方法学在关键路径延时调整、数据路径优化以及低功耗优化等问题的解决方法,并探讨如何将新的设计流程结合到原有项目开发中等问题。最终,高阶综合设计的RTL,在28 nm工艺下综合实现频率为2.5 GHz、面积为28 211μm^2,基本满足高性能微处理器的开发要求,增强了在项目中更加广泛地使用新设计方法学的信心。Double-precision floating-point multiplication parts is one of the most important unit of high performance CPU. This arti-cle describes the use of Cadence Stratus HLS tools in 28 nm process design and implement double-precision floating-point multi-plication. The frequency of this multiplication is 2.5 GHz, and its area is 28 211 square micrometers, which almost meets the re-quirements of high performance microprocessor development. The experiences of this work enhance the confidence of the more wide-ly using of the new design methodology in our project.

关 键 词：高阶综合 HLS 双精度浮点乘法 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]