基于FPGA的DDR3六通道读写防冲突设计  

Anti-conflict design for reading and writing of DDR3 six channels based on FPGA

作　　者：张凤麒 张延彬[1] 王忠勇[1] Zhang Fengqi;Zhang Yanbin;Wang Zhongyong(Industrial Technology Research Institute,Zhengzhou University,Zhengzhou 450000,Chin)

机构地区：[1]郑州大学产业技术研究院,河南郑州450000

出　　处：《电子技术应用》2018年第7期68-71,80,共5页Application of Electronic Technique

摘　　要：为了解决期货行情数据加速处理中多个通道同时访问DDR3时出现的数据读写冲突问题,实现了一种基于FPGA的DDR3六通道读写防冲突设计,完成了对单片DDR3内存条的多通道实时访问控制需求。通过ChipScope工具采样结果证明了设计的可行性,提高了并行处理的速度,极大程度地降低了期货行情数据处理中行情计算的时间开销,最高通道速率可达5.0 GB/s以上,带宽利用率可达80%以上,在多通道数据读写应用中具有很高的实用价值。In order to solve the problem of data conflict of reading and writing when multiple channels access DDR3 at the same time in the acceleration processing of futures market data, an anti-conflict design for reading and writing of DDR3 six channels based on FPGA is implemented and the requirement of multiple channels ′ real-time access control for monolithic DDR3 memory bar is completed. The result of Chip Scope sampling proves the feasibility of the design, it improves the parallel processing speed and reduces the prices of time overhead in the calculation of futures market data processing. The highest channel rate can reach more than 5. 0 GB/s and the bandwidth utilization rate can reach more than 80 %. The design has a very high practical value in the application of multiple channels ′ reading and writing.

关 键 词：多通道 防冲突 DDR3 FPGA 

分 类 号：TP334.4[自动化与计算机技术—计算机系统结构]