应用于FFT处理器的新型串接CSD常数乘法器设计  

A Novel Design of Cascade CSD Constant Multiplier for FFT

作　　者：于建[1] YU Jian(Physics and Electronics College,Hebei Normal University for Nationalities,Chengde 067000,Chin)

机构地区：[1]河北民族师范学院物理电子学院,河北承德067000

出　　处：《电讯技术》2018年第8期976-980,共5页Telecommunication Engineering

基　　金：河北省承德市应用技术研究与开发项目(20155008)

摘　　要：快速傅里叶变换(FFT)广泛应用于正交频分复用(OFDM)系统的调制与解调中。FFT的输出需要输入序列与旋转因子(TF)进行复数乘法运算,由于正则有符号数(CSD)常数乘法器实现简单、硬件开销小,常用于此类复数乘法运算,但随着旋转因子常数值个数的增加,其硬件开销会成倍增长。为了降低硬件开销,利用参数分解减少常数值个数的方法,提出了一种新型串接CSD常数乘法器。仿真结果显示对比常用的布斯乘法器,该新型串接CSD常数乘法器设计方案实现与旋转因子Wi128、Wi256以及Wi512进行复数乘法运算的硬件资源消耗分别减少41%、34%和25%。Fast Fourier Transform（FFT） is widely used in the modulation and demodulation of an Orthogonal Frequency Division Multiplexing（OFDM） system.FFT requires the complex multiplication of the input sequence and different twiddle factor（TF）.A Canonical Signed Digit（CSD） constant multiplier is always adopted to achieve the complex multiplication since it has simple structure and low hardware-cost.However,the hardware-cost has doubled and redoubled as the increasing number of TF′s constant values.In order to reduce hardware-cost,a novel cascade CSD constant multiplier is proposed by using the parameter decomposition method to decrease the number of constant values.The simulation result shows that the hardware-cost of complex multiplication with Wi128,Wi256 and Wi512 reduces 41%,34%,25%,respectively in comparison with that of commonly-used Booth multiplier.

关 键 词：CSD常数乘法器 布斯乘法器 傅里叶变换 旋转因子 

分 类 号：TN47[电子电信—微电子学与固体电子学]