解复用处理电路中成帧器模块的设计与仿真  

Design and Simulation of Framer Module in Demultiplexing Processing Circuit

作　　者：韩美林 乔成芳 HAN Meilin;QIAO Chengfang(School of Electronic Information and Electrical Engineering,Shangluo College,Shangluo 72600)

机构地区：[1]商洛学院电子信息与电气工程学院,商洛726000

出　　处：《计算机与数字工程》2018年第8期1664-1667,共4页Computer & Digital Engineering

基　　金：国家自然科学基金项目(编号:21703135);商洛市科学技术研究发展计划项目(编号:SK2017-42)资助

摘　　要：由于解复用电路中从高速的串行数据中恢复出来的不同类型的数据只是按照顺序以各自的bit宽度重新放置[1],并没有按照正确的帧格式字节对齐,导致后续电路无法直接使用这样的数据进行后续处理[2]。为了解决这一问题,设计了解复用处理电路中的成帧器模块。通过仿真验证了该成帧器的正确性,实验结果表明,该电路能够准确地完成帧头字符定位检测[3~4]。ince the different types of data recovered from the high-speed serial data in the demultiplexing circuit are merely re-placed in their respective bit widths in order and are not aligned in the correct frame format,resulting in subsequent circuits that can not directly use Data for follow-up. In order to solve this problem,this paper designs the framer module in the demultiplexing processing circuit. The correctness of the framer is verified by simulation. The experimental results show that the circuit can accurately detect the position of frame header.

关 键 词：解复用电路 成帧器 帧头字符定位 

分 类 号：TN929[电子电信—通信与信息系统]