基于FPGA的虚拟网络功能数据包处理加速架构  

Data Packet Processing Acceleration Architecture for Virtual Network Function Based on FPGA

作　　者：范宏伟 胡宇翔[1] 兰巨龙[1] FAN Hongwei,HU Yuxiang,LAN Julong(National Digital Switching System Engineering and Technology Research Center, Zhengzhou 450002, Chin)

机构地区：[1]国家数字交换系统工程技术研究中心,郑州450002

出　　处：《计算机工程》2018年第8期112-119,126,共9页Computer Engineering

基　　金：国家高技术研究发展计划项目(2015AA016102);国家自然科学基金创新研究群体项目(61521003);国家网络空间安全专项课题(2017YFB0803204)

摘　　要：针对虚拟网络功能(VNF)的数据包处理性能较差的问题,提出一种基于现场可编程门阵列(FPGA)的通用硬件加速器(GHA)架构。GHA架构在动态可重构FPGA上实现数据包处理流水线,提高VNF吞吐量并保证不同VNF加速器之间的独立性。采用基于离散粒子群优化算法的加速资源优化分配策略,实现加速收益的最大化。实验结果表明,GHA架构能将VNF的吞吐量提升50.7倍,加速资源分配策略优化率达到24.5%。In order to improve the packet processing performance of Virtual Network Function（VNF）,this paper comes up with a Field Programmable Gate Array（ FPGA）-based General Hardware Accelerator（ GHA） architecture. The GHA architecture implements the packet processing pipeline on a dynamically reconfigurable FPGA,increasing VNF throughput and ensuring independence between different VNF accelerators. The Discrete Particle Swarm Optimization（ DPSO）algorithm is utilized to optimize the allocation of acceleration resources. Experimental results indicate that GHA architecture can increase the throughput of VNF by 50. 7 times approximately,and the optimization rate of the acceleration resource allocation strategy can reach 24. 5%.

关 键 词：虚拟网络功能 通用硬件加速器 动态可重构 加速资源分配优化 离散粒子群优化 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]