基于CCSDS标准的串行级联卷积码高速并行译码方法  被引量:1

High Throughput Parallel Decoding Method for Serial Concatenated Convolutional Codes Based on CCSDS Standard

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作  者:李林涛 刘昊[2] 张舒义 刘元安[1] LI Lin-tao;LIU Hao;ZHANG Shu-yi;LIU Yuan-an(School of Electronic Engineering,Beijing University of Posts and Telecommunications,Beijing 100876,China;School of Information and Electronics,Beijing Institute of Technology,Beijing 100081,China)

机构地区:[1]北京邮电大学电子工程学院,北京100876 [2]北京理工大学信息与电子学院,北京100081

出  处:《北京理工大学学报》2018年第7期733-738,共6页Transactions of Beijing Institute of Technology

基  金:国家自然科学基金资助项目(61327806;61501028)

摘  要:针对CCSDS标准中串行级联卷积码(SCCC)的自适应编码调制方式的定义,分析比较了Log-MAP算法和基于乘性修正的Max-Log-MAP算法的译码性能和实现复杂度;提出了一种可支持多种编码方式的通用、低复杂度、高编码增益的并行译码方法.基于FPGA硬件平台进行原理验证,实现了一个可同时支持8种编码方式的高速并行、高吞吐量、低时延的SCCC译码器,译码器最高吞吐量可达300 Mbit/s.According to serial concatenated convolutional codes(SCCC)adaptive coded modulation scheme defined in the consultative committee for space data systems(CCSDS)standard,Log-MAP algorithm and Max-Log-MAP algorithm with multiplicative correction were analyzed and compared in the decoding performance and implementation complexity.On the basis of these studies,aparallel decoding method with low complexity and high coding gain was proposed in this paper.Furthermore,ageneral and parallel decoding structure,supporting a variety of coded modulation schemes,was provided.Finally,based on FPGA hardware platform,a high-speed,parallel and high-throughput SCCC decoder was designed for eight coded modulation schemes.The testing result indicates that the maximum throughput can be up to 300 Mbit/s.

关 键 词:串行级联卷积码(SCCC) LOG-MAP 并行译码 

分 类 号:TN911.2[电子电信—通信与信息系统]

 

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