一种适用于三维芯片间时钟同步的全数字延时锁定环设计  

Design of ADDLL for 3D-IC Die-to-Die Clock Synchronization

作　　者：叶云飞[1,2] 吴宁[1] 葛芬[1] 周芳[1] YE Yun-fei;WU Ning;GE Fen;ZHOU Fang(College of Electrical and Information Engineering,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China;College of Innovation,Nanjing Institute of Railway Technology,Nanjing 210031,China)

机构地区：[1]南京航空航天大学电子信息工程学院,江苏南京210016 [2]南京铁道职业技术学院创新学院,江苏南京210031

出　　处：《微电子学与计算机》2018年第9期52-54,共3页Microelectronics & Computer

基　　金：国家自然科学基金(61376025);江苏省高校自然科学基金(17KJB510033)

摘　　要：本文提出了一种适用于三维集成电路芯片间时钟同步的全数字延时锁定环设计.在给定的三维集成电路中,该全数字延时锁定环采用可变逐次逼近寄存器控制器设计来缩短锁定时间,以消除谐波锁定问题并拓宽工作频率范围,实现硅过孔引起的延时偏差可容忍和垂直堆叠芯片间时钟信号同步.整个设计采用TSMC 65nm CMOS低功耗工艺实现.仿真结果显示在工艺角最坏情况下最高工作频率是833MHz(SS,125℃,1.08V),在工艺角最好情况下最低工作频率是167MHz(FF,-40℃,1.32V),整个工作频率范围内最长锁定时间固定为103个输入时钟周期,在典型工艺角下功耗为0.8mW@833 MHz(TT,25℃,1.2V).版图有效核心面积为0.018mm2.In this paper,an all-digital delay-locked loop（ADDLL）for die-to-die clock synchronization of threedimensional integrated circuit（3 D-IC）is presented.The proposed ADDLL can endure the delay variations between through silicon vias and synchronize the clock signals between vertically stacked dies of the given 3 D-IC.In order to solve the harmonic lock problem and widen the operating frequency,the circuit shortened the lock process by the use of variable successive approximation register-controlled scheme.The presented ADDLL is implemented using the TSMC 65 nm CMOS low power technology,and the simulation results show that the highest operating frequency is833 MHz at the worst case（SS,125℃,1.08 V）,the lowest operating frequency is 167 MHz at the best case（FF,-40 ℃,1.32 V）,the longest lock time is 103 cycles of the input clock,and the power consumption is estimated to be 0.8 mW@833 MHz at the typical case（TT,25 ℃,1.2 V）.The area of the ADDLL per die is 0.018 mm2.

关 键 词：全数字延时锁定环 时钟同步 三维集成电路 

分 类 号：TN4[电子电信—微电子学与固体电子学]