粗粒度可重构处理器的系统级功耗建模  

System Level Power Modeling for Course-Grained Reconfigurable Processor

作　　者：穆昌根 赵仲元[1] 绳伟光[1] 毛志刚[1] MU Chang-gen;ZHAO Zhong-yuan;SHENG Wei-guang;MAO Zhi-gang(School of Microelectronies,Shanghai Jiao Tong University,Shanghai 200240,China)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240

出　　处：《微电子学与计算机》2018年第9期70-73,78,共5页Microelectronics & Computer

基　　金：国家高技术研究发展计划(2012AA012702);上海交通大学"科技创新专项资金"(YG2014MS70)

摘　　要：本文针对粗粒度可重构结构,提出一种可根据不同结构参数进行拓展的系统级功耗建模方法.该方法采用层次描述的方法,分别从体系结构、电路和工艺层建立功耗模型,再利用线性模型计算出系统的整体功耗.对比仿真和实测数据的误差,验证了该建模方法的有效性.在探索粗粒度可重构架构的早期,可以应用该方法来评估可重构处理器的功耗.In this paper,we propose a system-level power modeling method that can be extended according to different structural parameters for coarse-grained reconfigurable architecture.The method described by the level of methods,respectively,from the architecture,circuit and technology level to establish the power model,and then use the linear model to calculate the overall power consumption of the system.Contrasting the errors of simulation and measured data,the validity of this modeling method is verified.Early in exploring coarse-grained reconfigurable architectures,this approach can be applied to evaluate the power consumption of reconfigurable processors.

关 键 词：粗粒度可重构处理器 系统级功耗建模 动态功耗 静态功耗 

分 类 号：TN47[电子电信—微电子学与固体电子学]