一种反熔丝FPGA应用设计故障  

An Application Design Fault of Antifuse FPGA

作　　者：杜涛[1] 许百川 李威[1] 晁醒 吴方明 DU Tao;XU Bai-chuan;LI Wei;CAO Xing;WU Fang-min(State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China,Chengdu,610054,China)

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《微电子学与计算机》2018年第9期108-112,117,共6页Microelectronics & Computer

基　　金：国家自然科学基金(61404021)

摘　　要：由于反熔丝FPGA架构和实现原理的特殊性,反熔丝FPGA应用设计在物理实现时,存在一种易于发生、故障现象不稳定且具有一定隐蔽性的时序逻辑故障.通过对故障现象、诱因、原理的深入剖析,发现该应用设计故障与反熔丝FPGA的散出能力限制(Fanout limit)关联,并有针对性地提出了根除故障因素的解决方案.通过实测验证表明,本解决方案能有效消除该类应用设计故障.Due to the particularity of the architecture and implementation principle of the antifuse FPGA,there is a kind of sequential logic fault which is prone to occur,unstable in the fault phenomenon and has a certain concealment when the application design is implemented in the antifuse FPGA.Through in-depth analysis of the fault phenomenon,causes and principles,it is found that the application design fault is related to the drive capability（Fanout limit）of the antifuse FPGA.Aiming at the fault characteristics,a set of solutions to eradicate the fault factors are proposed.The experimental results show that the solutions can effectively eliminate the application design fault.

关 键 词：反熔丝FPGA 应用设计故障 扇出能力限制 时钟偏斜 寄存器掉链 

分 类 号：TN702[电子电信—电路与系统]