FPGA跨时钟域信号同步设计方法研究  

Signal Synchronization Design Method of Cross Clock Domain in FPGA

作　　者：宋文强[1] 胡毅 Song Wenqiang;Hu Yi(The Fifth Electronics Research Institute of Ministry of Industry and Information Technology,Guangzhou 510 610,China;CEPREI Laboratory)

机构地区：[1]工业和信息化部电子第五研究所,广州510610 [2]重庆赛宝工业技术研究院

出　　处：《单片机与嵌入式系统应用》2018年第9期24-27,81,共5页Microcontrollers & Embedded Systems

摘　　要：随着FPGA功能越来越复杂,其内部设计经常包含多个异步时钟,将FPGA分割为多个时钟域,不同时钟域之间进行的数据和信号通信引入了跨时钟域问题。本文主要阐述了跨时钟域设计常见问题、跨时钟域信号同步方案,在此基础上从验证工程师角度出发,介绍了如何进行跨时钟域验证的方法和步骤,为更好地进行跨时钟域分析提供了一种思路。With the increasing complexity of the FPGA,most of designs based on FPGA containmultiple asynchronous clocks dividing into multiple clock domains.The cross clock domain problem is introduced when the data and signal communication between different clock domains.The common problems and signal synchronization scheme of cross clock domain are introduced.Based on this,the method and procedure of how to verify the time domain is presented.

关 键 词：FPGA 跨时钟域 亚稳态 同步设计 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]