40 nm工艺芯片中低k介质剪切失效分析  

Analysis of Shear Failures of the Low-k Material in the Chips with 40 nm Technology

作　　者：杨辰 王珺[1] 王磊 余可航 Yang Chen;Wang Jun;Wang Lei;Yu Kehang(Department of Materials Science,Fudan University,Shanghai 200433,China;National Center for Advanced Packaging Co.,Ltd.,Wuxi 214135,China)

机构地区：[1]复旦大学材料科学系,上海200433 [2]华进半导体封装先导技术研发中心有限公司,江苏无锡214135

出　　处：《半导体技术》2018年第9期708-713,共6页Semiconductor Technology

基　　金：国家自然科学基金资助项目(61774044);国家科技重大专项资助项目(2017ZX02315005);新型显示技术及应用集成教育部重点实验室(上海大学)基金资助项目

摘　　要：90 nm节点及以下的芯片在回流组装中,材料热失配引起的凸点剪切易导致低介电常数（k）布线介质层中发生断裂失效,即芯片封装交互影响问题。通过单个凸点的剪切试验,结合凸点下方的布线层失效分析,评估芯片布线层可靠性;并采用有限元分析方法对一款40 nm节点芯片的凸点进行剪切模拟,用子模型分析了凸点受剪切时,布线层中微裂纹的裂尖能量释放率（ERR）随剪切高度、剪切力和微裂纹长度的变化。研究结果表明：模拟与试验结果相符,裂尖ERR随剪切高度、剪切力、微裂纹长度的增加而升高,降低凸点剪切高度有利于减小低k材料断裂的可能性。In the reflow assembly of chips with 90 nm node and below,the low dielectric constant（ k） layer in back end of line（ BEOL） is prone to crack and failure due to bump shear caused by material thermal mismatch,that is the chip packaging interaction problem. A shear test for a single bump and a followed failure analysis of the wiring layer under bumps were performed to evaluate the reliability of the chip wiring layer. The bump shear of a chip with 40 nm node was simulated by finite element analysis method. And a sub-model was applied to analyze the changes of the energy release rate（ ERR） at crack tips of the microcracks in the wiring layer with shear height,shear force and microcrack length when the bumps were sheared. The research results show that the simulation results are consistent with the experimental results. The ERR at crack tips increases with the increase of shear height,shear force and microcrack length. Decreasing the shear height of bumps is helpful to reduce the possibility of low-k materials fracture.

关 键 词：芯片封装交互影响 有限元分析 子模型 剪切实验 能量释放率(ERR) 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]