Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory  

作　　者：Jin-Shun Bi Kai Xi Bo Li Hai-Bin Wang Lan-Long Ji Jin Lil and Ming Liu 毕津顺;习凯;李博;王海滨;季兰龙;李金;刘明(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China;School of Internet of Things Engineering,Hohai University,Changzhou 213022,China)

机构地区：[1]Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China [2]University of Chinese Academy of Sciences, Beijing 100049, China [3]School of Internet of Things Engineering, Hohai University, Changzhou 213022, China

出　　处：《Chinese Physics B》2018年第9期615-619,共5页中国物理B（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Grant No.616340084);the Youth Innovation Promotion Association of CAS(Grant No.2014101);the International Cooperation Project of CAS;the Austrian-Chinese Cooperative R&D Projects(Grant No.172511KYSB20150006)

摘　　要：Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.

关 键 词：heavy ion Flash memory single event upset annealing 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TN386[自动化与计算机技术—计算机科学与技术]