一种混合结构的新型近似加法器  

A novel approximate adder with hybrid structures

作　　者：王保坤 班恬[1] WANG Bao-kun;BAN Tian(School of Electronic and Optical Engineering,Nanjing University of Science and Technology,Nanjing 210094,China)

机构地区：[1]南京理工大学电子工程与光电技术学院,江苏南京210094

出　　处：《电子设计工程》2018年第18期1-5,共5页Electronic Design Engineering

基　　金：国家自然科学基金资助项目(61401205)

摘　　要：近似计算是超大规模集成电路(very large scale integration circuit,VLSI)设计与测试的新型设计方式。基于近似的思想,运算电路通过适当地牺牲运算精度来提高容错应用系统的性能。本文提出了一种具有混合结构的新型近似加法器,它可以产生不同精度的运算结果。本文对该加法器利用28纳米的全耗尽绝缘体上硅(fully-depleted silicon-on-insulator,FD-SOI)的工艺技术进行了电路综合。实验结果表明它的平均误差距离(mean error distance)优于其他近似加法器设计。相对于行波进位加法器(ripple carry adder,RCA),该近似加法器的速度比其快1.35倍,功耗也节约了16%。最后,本文通过该近似加法器在DCT/IDCT程序中的运用证明了其实际应用价值。Approximate computing is a new design paradigm in VLSI（very large scale integration circuit）design and test. Based on the thought of approximation,arithmetic circuit properly sacrifices its accuracy to improve the performance of fault-tolerant application system. In this paper,we propose a novel approximate adder with a hybrid structure which produces results of different precision. The proposed adder is synthesized by utilizing 28 nm FD-SOI（fully-depleted silicon-on-insulator）technology. The experimental results shows that it excels the existing approximate adder designs regarding mean error distance. Compared to RCA（ripple carry adder）,the approximate adder is 1.35 times faster and saves power consumption by 16%. The efficiency is also validated by its application in DCT/IDCT procedures.

关 键 词：集成电路技术 近似加法器 容错 DCT/ICT 

分 类 号：TN492[电子电信—微电子学与固体电子学]