基于JESD204B的高速串行数据收发接口设计  

Design of High Speed Serial Data Transceiver Interface Based on JESD204B

作　　者：徐凤萍[1] 龚至诚 王巍[1] XU Feng-ping;GONG Zhi-cheng;WANG Wei(Jiangsu Automation Research Institute,Lianyungang 222061,China;Jiangsu University of Science and Technology,Zhenjiang 212003,China)

机构地区：[1]江苏自动化研究所,江苏连云港222061 [2]江苏科技大学电子信息学院,江苏镇江212003

出　　处：《指挥控制与仿真》2018年第5期129-132,共4页Command Control & Simulation

摘　　要：目前的ADC/DAC多采用并行传输接口,在进行数据采用分析时,存在着串扰高、传输同步困难的一系列难题,为了解决这些问题,推出了以JESD204B为基础的高速串行数据传输接口。接口基于Xilinx公司的Virtex-7系列FPGA为核心控制单元设计电路,对于单通道来讲,其对应的传输速率是6Gb/s,进行有关信息收发检测,证明了传输信息的同步性以及整个方案的可行性。结果证明,基于JESD204B的串行传输办法不仅有效化解了并行传输存在的缺陷,同时有效降低了PCB布线难度,并且节约了成本。In order to solve the problems of large crosstalk and difficult synchronization between the parallel sampling data intraditional ADC/ DAC applications, a data transceiver interface based on high-speed serial protocol JESD204B is designed.With Xilinx company V7 series FPGA as the core control unit circuit design, the single channel transmission rate of 6Gb / sunder the condition of complete data transceiver test, verify the feasibility of synchronization, accuracy and overall scheme ofdata transmission in the process of. The design results show that this serial transmission mode not only solves many problemscaused by parallel transmission, but also reduces the complexity of PCB routing, reduces the number of boards and saves thecost.

关 键 词：高速串行协议 JESD204B 数据传输接口设计 FPGA 模数/数模转换器 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]