基于FPGA的16×16点阵模块控制器设计  

Design of 16×16 Dot Matrix Module Controller Based on FPGA

作　　者：乔广欣 李亚峻[1] 李松 杨堃斌 于宝 QIAO Guangxin;LI Yajun;LI Song;YANG Bin;YU Baokun(College of Electronic Information and Automation,Tianjin University of Science ＆ Technology,Tianjin 300222,China)

机构地区：[1]天津科技大学电子信息与自动化学院,天津300222

出　　处：《天津科技》2018年第10期59-61,65,共4页Tianjin Science & Technology

基　　金：天津科技大学大学生实验室创新基金(No.1702A203);全国高校实验室工作研究会学术研究计划(No.SY2015Z059)

摘　　要：为了减少芯片IO口的占用,由74HC138驱动点阵行、由74HC595驱动点阵列。为了用FPGA芯片控制点阵显示,用VHDL语言编程实现。介绍了16×16点阵模块的硬件连接,分析了74HC595的工作时序和点阵列数据的存储与调用,进而提出点阵行列控制器的VHDL程序设计方法,用于实现装载新数据、选通点阵行、16位数据先低位后高位的串行输出、产生74HC595的时钟信号和输出锁存信号。将Basys2开发板与点阵模块相连,将程序下载到FPGA上,实现了16×16点阵的显示,验证了设计的正确性,具有实际应用价值。74HC138 and 74HC595 were used to drive dot matrix row and column respectively to reduce the occupation of the chip IO port. Programming was implemented using VHDL language to control the dot matrix display via FPGA chip. This paper introduces hardware connection of the 16 × 16 dot matrix module, and analyzes the timing of the 74HC595 and storage and transfer of dot matrix column data. A VHDL program design method for dot matrix row and column controller was proposed to implement new data loading, the strobe dot matrix row, 16-bit data serial output according to the low first and then high, the generation of 74HC595 clock signal and output latch signal. The dot matrix module is connected to the Basys2 development board, and the program is downloaded to the FPGA.A 16 × 16 dot matrix display is implemented, which verifies the correctness of the design. The design has practical application value.

关 键 词：现场可编程门阵列 VHDL语言 点阵显示 74HC595芯片 74HC138芯片 

分 类 号：TP332.1[自动化与计算机技术—计算机系统结构]