基于74LS112的同步五进制加法计数器的设计与仿真  

Design and simulation of synchronous five-band addition counter based on 74LS112

作　　者：季丽琴[1] JI Liqin(School of Electronics ＆Information,Suzhou Chien-Shiung Institute of Technology,Taicang Jiangsu 215400,China)

机构地区：[1]苏州健雄职业技术学院电子信息学院,江苏太仓215400

出　　处：《智能计算机与应用》2018年第6期124-126,共3页Intelligent Computer and Applications

摘　　要：根据同步时序逻辑电路设计思路,利用集成边沿JK触发器74LS112设计的同步五进制加法计数器,借助Multism10进行仿真调试。该计数器主要由脉冲信号模块、触发模块和计数显示模块组成,可实现0～4共计5种计数状态。实验结果表明,该计数器的设计合理,不仅完美体现了理论推导与仿真实践的高度一致,而且可以作为设计任意进制同步加法计数器的参考。According to the idea of design of synchronous sequential logic circuit, a synchronous five band addition counter isdesigned with integrated edge JK flip-flop 74LS112, and the simulation debugging is carried out with the aid of Multism10. Thiscounter is mainly composed of pulse signal module, trigger module and counting display module. It can realize 5 counting statesfrom 0 to 4. The experimental results show that the design of the counter is reasonable, which not only embodies the perfectagreement between theoretical deduction and simulation practice, but also can be used as a reference for the design of arbitrarysynchronous addition counter.

关 键 词：74LS112 加法计数器 MULTISIM10 

分 类 号：TH724[机械工程—仪器科学与技术]