基于FPGA内部高速缓存的质谱数据传输系统设计  

Design of mass spectrometry data transmission system based on FPGA internal cache

作　　者：陈飞华 杨继伟 罗群英 Chen Feihua;Yang Jiwei;Luo Qunying(Focused Photonocs（Hangzhou）Inc.,Hangzhou,310052,China;Arcvideo Technologies Co.,Ltd.,Hangzhou,Zhejiang,310052,China)

机构地区：[1]聚光科技(杭州)股份有限公司,浙江杭州310052 [2]杭州当虹科技股份有限公司,浙江杭州310052

出　　处：《现代科学仪器》2018年第3期17-21,共5页Modern Scientific Instruments

摘　　要：四极杆质谱仪与快速气相色谱仪的联用极大地提高了仪器的快速定性和定量能力.但是,与快速气相色谱仪联用的四极杆质谱仪必须具备快速质量扫描能力和很高的工作占空比,这对质谱数据传输系统提出了很高的要求.为减少两次质谱扫描之间等待数据传输的死时间,提高四极质谱仪的工作占空比,本文提出一种基于FPGA内部高速缓存的质谱数据传输系统,实现外部SDRAM和以太网口之间的数据实时传输.在FPGA中设立了2个容量为1M的高速缓存,高速A/D采集得到的质谱数据首先被存储在内部RAM中,然后通过时序调度将数据分块传输至高速缓存SDRAM中,进一步轮流访问高速缓存并将数据通过以太网口传输至上位机.本文中的主控制器FPGA选用Altera公司的EP4CE30F23C7,外部SDRAM则采用ISSI公司的IS42S16160G,基于AlteraSOPCBuilder设计了SDRAM和RAM控制、Avalon总线控制器和主从设备控制端口.仿真及实验结果表明,本控制系统将四极杆质谱的数据传输死时间由以前的100ms缩短到10ms,四极杆质谱仪的工作占空比由50%提升至90%以上,同时大幅提升了四极杆质谱的扫描速率.The combination of quadrupole mass spectrometer and fast gas chromatograph has greatly improved the rapid qualitative and quantitative ability of the instrument. However, the quadrupole mass spectrometer combined with the fast gas chromatograph must have fast mass scanning ability and high duty cycle, which put forward high requirements for mass spectrometry data transmission system. In order to reduce the dead time of data transmission between two mass spectrometry scans and improve the duty cycle of quadrupole mass spectrometer, a mass spectrometry data transmission system based on internal cache of FPGA is proposed to realize real-time data transmission between external SDRAM and Ethernet port. Two 1M caches are set up in the FPGA. The mass spectrometry data collected by high-speed A/D is frst stored in the RAM, and then transmitted to the cache by block transmission through timing scheduling. Then the cache is accessed in turn and the data is transmitted to the host computer through the Ethernet port. In this paper, EP4CE30F23C7 of Altera company is used as the main controller of FPGA, ISSI company is used for external SDRAM IS42S16160G, based on Altera SOPC Builder designed SDRAM and RAM control, Avalon bus controller and master-slave device control port. The results of simulation and experiment show that the dead time of quadrupole mass spectrometer is shortened from 100 ms to 10 ms, the duty cycle of quadrupole mass spectrometer is increased from 50% to 90%, and the scanning speed of quadrupole mass spectrometer is greatly increased.

关 键 词：四极杆 SDRAM SOPC AVALON总线 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]