H.265帧内模式判决并行计算方法研究与实现  

Study and Implementation in Parallel Method of H.265 Intra Mode Decision

作　　者：李申 柴志雷[1,2] 严伟 夏珺[1] 赵建斌 LI Shen;CHAI Zhi-lei;YAN Wei;XIA Jun;ZHAO Jian-bin(School of Internet of Things Engineering,Jiangnan University,Wuxi 214122,China;State Key Laboratory of Mathematical Engineering and Advanced Computing,Wuxi 214125,China;School of Software ＆ Microelectronics,Peking University,Beijing 102600,China)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]数学工程与先进计算国家重点实验室,江苏无锡214125 [3]北京大学软件与微电子学院,北京102600

出　　处：《小型微型计算机系统》2018年第11期2523-2527,共5页Journal of Chinese Computer Systems

基　　金：国家重点研发计划专项(2016YFC0801001)资助;数学工程与先进计算国家重点实验室开放基金项目(2017A08)资助

摘　　要：针对H.265帧内编码算法编码速度慢的问题,基于现场可编程逻辑门阵列(FPGA)设计了一种并行帧内模式判决架构.首先通过理论推导,证明可以将多层次多尺度编码块的模式判决问题转化为单一层次多个小尺度编码块模式判决的叠加问题;其次,在编码块内部通过细粒度并行实现快速模式判决,在编码块之间通过窗口流水方式实现快速处理;最终在FPGA上设计并实现了该帧内快速模式判决架构.实验结果表明,本文算法最高可达到93.6x的加速比,且编码后的视频质量损失较小(PSNR平均降低0.71dB).A parallel mode decision architecture based on Field-Programmable Gate Array（FPGA）is designed for the problem of slow coding speed of H.265 intra frame coding algorithm.Firstly,problem of multi-scale mode decision is improved by dividing into the superposition problem of single-level small scale mode decision with theoretical derivation;secondly,fine-grained parallel implementation is used in single coding unit for fast mode decision while pipelined window buffer is being used to speed up processing time between coding units;Finally,the architecture was designed and implemented on FPGA.The experimental results show that the speed up ratio of the design is up to 93.6 with a little quality drop（PSNR decreased 0.71dB in average）.

关 键 词：视频编码 FPGA 模式判决 编码块叠加 细粒度并行 

分 类 号：TP37[自动化与计算机技术—计算机系统结构]