Berger code based concurrent online self-testing of embedded processors  

作　　者：G.Prasad Acharya M.Asha Rani 

机构地区：[1]Department of ECE, Sree Nidhi Institute of Science and Technology [2]Department of ECE, JNTUH College of Engineering, JNTUH University

出　　处：《Journal of Semiconductors》2018年第11期68-73,共6页半导体学报（英文版）

摘　　要：We propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset(SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self-testable architecture is proposed and integrated in 32-bit DLX reduced instruction set computer(RISC) processor on a single silicon chip. The proposed concurrent test methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self-testing to detect temporary faults.We propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset(SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self-testable architecture is proposed and integrated in 32-bit DLX reduced instruction set computer(RISC) processor on a single silicon chip. The proposed concurrent test methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self-testing to detect temporary faults.

关 键 词：single event upset Berger code DLX RISC online testing 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]