一种12位20 kS/s功耗调制算法SAR ADC  

A 12 bit 20 kS/s Power-Shaping SAR ADC

作　　者：吴霜毅[1] 杜翎 WU Shuangyi;DU Ling(State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu 610054, P. R. ChinaTwenty-first Century （Beijing） Microelectronics Technology Co. , Ltd. , Chengdu 610051, P. R. China)

机构地区：[1]电子薄膜与集成器件国家重点实验室,成都610054 [2]二十一世纪(北京)微电子技术有限公司成都分公司,成都610051

出　　处：《微电子学》2018年第5期565-569,共5页Microelectronics

摘　　要：针对时域稀疏信号中的心电信号(ECG)、脑电信号(EEG)在大部分时间内幅度变化缓慢且周期性变化的特性,提出了一种带信号区间预测窗口的功耗调制型逐次逼近模数转换算法。采用该算法,可大幅减少SAR ADC中稀疏信号在低频部分的平均量化功耗,实现整体功耗的降低。在此理论基础上,设计了一种非二进制冗余校正、功耗调制型12位20kS/s SAR ADC。该ADC采用55nm CMOS工艺进行流片,在0.6V电源电压下,功耗低至204 nW,功耗优值FoM最低为6.28 fJ/(conv·step)。A power-shaping successive approximation analog-to-digital conversion（SAR ADC）algorithm for time-domain sparse signal was designed. Because the sparse signal as electrocario signal（ECG） or electroencephalogram signal（EEG）changed slowly and periodically in the time domain,the SAR ADC utilized a signal range predication window to save ADC＇s power consumption according to the sparse characteristics of the input signal.The algorithm significantly reduced the average quantization power consumption for converting the low-frequency part of the input sparse signal in the SAR ADC.As a result,the whole power consumption of the ADC was decreased as well.Based on the power-shaping theory,a 12 bit 20 kS/s non-binary redundancy correction and power-shaping SAR ADC prototype chip was implemented.The ADC chip was fabricated in a 55 nm CMOS process.It dissipated as low as 204 nW at 0.6 Vpower supply,and the best figure-of-merit achieved 6.28 fJ/（conv·step）.

关 键 词：逐次逼近型ADC 功耗调制型ADC 量化区间预测 心电信号 

分 类 号：TN792[电子电信—电路与系统] TN432