Analysis of tail bits generation of multilevel storage in resistive switching memory  

作　　者：Jing Liu Xiaoxin Xu Chuanbing Chen Tiancheng Gong Zhaoan Yu Qing Luo Peng Yuan Danian Dong Qi Liu Shibing Long Hangbing Lv Ming Liu 刘璟;许晓欣;陈传兵;龚天成;余兆安;罗庆;袁鹏;董大年;刘琦;龙世兵;吕杭炳;刘明(1 School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China 2Laboratory of Nano-Fabrication and Novel Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China)

机构地区：[1]School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China [2]Laboratory of Nano-Fabrication and Novel Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

出　　处：《Chinese Physics B》2018年第11期626-629,共4页中国物理B（英文版）

基　　金：Project supported by the Ministry of Science and Technology of China(Grant Nos.2016YFA0203800,2016YFA0201803,and 2018YFB0407502);the National Natural Science Foundation of China(Grant Nos.61522408,61334007,and 61521064);Beijing Municipal Science&Technology Commission Program,China(Grant No.Z161100000216153);Huawei Data Center Technology Laboratory

摘　　要：The tail bits of intermediate resistance states（IRSs） achieved in the SET process（IRSS） and the RESET process（IRSR） of conductive-bridge random-access memory were investigated. Two types of tail bits were observed, depending on the filament morphology after the SET/RESET operation.（i） Tail bits resulting from lateral diffusion of Cu ions introduced an abrupt increase of device resistance from IRS to ultrahigh-resistance state, which mainly happened in IRSS.（ii） Tail bits induced by the vertical diffusion of Cu ions showed a gradual shift of resistance toward lower value. Statistical results show that more than 95% of tail bits are generated in IRSS. To achieve a reliable IRS for multilevel cell（MLC） operation, it is desirable to program the IRS in RESET operation. The mechanism of tail bit generation that is disclosed here provides a clear guideline for the data retention optimization of MLC resistive random-access memory cells.The tail bits of intermediate resistance states（IRSs） achieved in the SET process（IRSS） and the RESET process（IRSR） of conductive-bridge random-access memory were investigated. Two types of tail bits were observed, depending on the filament morphology after the SET/RESET operation.（i） Tail bits resulting from lateral diffusion of Cu ions introduced an abrupt increase of device resistance from IRS to ultrahigh-resistance state, which mainly happened in IRSS.（ii） Tail bits induced by the vertical diffusion of Cu ions showed a gradual shift of resistance toward lower value. Statistical results show that more than 95% of tail bits are generated in IRSS. To achieve a reliable IRS for multilevel cell（MLC） operation, it is desirable to program the IRS in RESET operation. The mechanism of tail bit generation that is disclosed here provides a clear guideline for the data retention optimization of MLC resistive random-access memory cells.

关 键 词：resistive random-access memory （RRAM） multilevel cell tail bits 

分 类 号：O4[理学—物理]