基于FPGA与DDR3缓存的PAL制式图像源产生模块设计与实现  

Design and Implementation of PAL Image Source Generating Module Based on FPGA and DDR3-SDRAM

作　　者：杨文豪 倪文龙 付强 孙舟 郭奇 钱宏文[1] YANG Wenhao;NI Wenlong;FU Qiang;SUN Zhou;GUO Qi;QIAN Hongwen(No.58 Research Institute,China Electronics Technology Group Corporation,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《实验室研究与探索》2018年第11期96-99,共4页Research and Exploration In Laboratory

摘　　要：为实现环境试验中产品关键性能的快速测试,模拟4路PAL制式摄像头并行输出,设计了基于FPGA与DDR3的图像源产生模块。将YCrCb格式图像源按照ITU-RBT. 656标准编码,采用ADV7393芯片实现PAL制式转换,通过分区缓存和等时轮转的方式,经由DDR3-SDRAM实现4路PAL制式图像的同步输出。经验证,该模块有效实现并行输出4路PAL制式图像数据,通过硬件电路的扩展,能够实现多台设备的4路图像源输入,进一步提高测试效率。To realize rapid test of the key performance of the products in the environment test, and simulate a 4-channel PAL camera output in parallel, an image source generating module based on FPGA and DDR3 was designed. The YCrCb format image source was encoded according to ITU-RBT.656 standard, and the ADV7393 chip was used to realize the PAL format conversion, the DDR3-SDRAM stored and outputted data by a method of partition storage and pipelined rotation. It has been proved that the module can effectively output 4 image sources in parallel, and by circuit expansion, the test efficiency can be strongly improved.

关 键 词：现场可编程门阵列 ITU-RBT.656编码 并行设计 DDR3-SDRAM 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]