Parallel Critical Path Tracing——A Fault Simulation Algorithm for Combinational Circuits  

作　　者：魏道政 

机构地区：[1]Institute of Computing Technology,Academia Sinica

出　　处：《Journal of Computer Science & Technology》1990年第2期156-163,共8页计算机科学技术学报（英文版）

基　　金：The project is supported by the National Natural Science Foundation of China.

摘　　要：Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostcomputer is m,then the parallel critical path tracing will be approximately m times faster than the originalone.Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to the parallel critical path tracing for functional block-level combinational circuits.If the word length of the host computer is m,then the parallel critical path tracing will be approximately m times faster than the original one.

关 键 词：A Fault Simulation Algorithm for Combinational Circuits Parallel Critical Path Tracing PATH SIMULATION 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]