A Hierarchical Reconfiguration Strategy for Bus-Based Multiprocessors  

作　　者：Ashish Pancholy Fidel Muradali Vinod K.Agarwal 

机构地区：[1]VLSI Design Laboratory,Department of Electrical,Engineering,McGill University

出　　处：《Journal of Computer Science & Technology》1990年第2期175-186,共12页计算机科学技术学报（英文版）

摘　　要：A method of providing redundancy to a class of bus-based multiprocessor arrays is discussed.The reconfiguration is hierarchical,providing global spare replacement at the array level and local reconfiguration within the spare block.Results of yield analysis performed on a 32 processor array are pres- ented.A method of providing redundancy to a class of bus-based multiprocessor arrays is discussed.The reconfiguration is hierarchical,providing global spare replacement at the array level and local reconfiguration within the spare block.Results of yield analysis performed on a 32 processor array are pres- ented.

关 键 词：A Hierarchical Reconfiguration Strategy for Bus-Based Multiprocessors PE 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]